From: Henry Styles <hes@sifive.com>
Date: Tue, 8 Aug 2017 05:03:35 +0000 (-0700)
Subject: Use AXI4 mem key
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=360fe7e2a9c8f9982d1822baf6e56002a3705f9a;p=sifive-blocks.git

Use AXI4 mem key
---

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 7d864e4..07f5562 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -24,7 +24,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
-      address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+      address = p(AXI4MemPortKey).address,
       resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,