From: Florent Kermarrec Date: Wed, 20 Nov 2019 18:24:40 +0000 (+0100) Subject: soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal X-Git-Tag: 24jan2021_ls180~844 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36107cdfd79752289b24fb6200a90094d78ad597;p=litex.git soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal --- diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 70133f39..e1964555 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -225,7 +225,7 @@ class S7PLL(XilinxClocking): config = self.compute_config() pll_fb = Signal() self.params.update( - p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, + p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq, @@ -319,7 +319,7 @@ class USPLL(XilinxClocking): config = self.compute_config() pll_fb = Signal() self.params.update( - p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, + p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq, @@ -355,7 +355,7 @@ class USMMCM(XilinxClocking): config = self.compute_config() mmcm_fb = Signal() self.params.update( - p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, + p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,