From: Connor Abbott Date: Thu, 5 Mar 2020 16:10:47 +0000 (+0100) Subject: freedreno: Cleanup event names X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36133a5434d38d8a4983df3fcd31b7e5dccf00cf;p=mesa.git freedreno: Cleanup event names It turns out that every *_TS event, i.e. every event which requires a seqno pointer, also allows generating an interrupt in the kernel, at least since a3xx. And furthermore these interrupts are named by the kgsl kernel driver and already in envytools. Therefore it's possible to map out what the *_TS events are with 100% certainty, given access to the hardware, by sending a CP_EVENT_WRITE with bit 31 set, unmasking all interrupts in the kernel, and logging which ones get hit. I've done this for a6xx, and I've also looked at the a5xx firmware, and the list of TS interrupts is the same as a6xx, so I have a pretty good idea of what the a5xx events are. I also fixed a few related things along the way: - VIZQUERY_END overlaps with WT_DONE_TS, but VIZQUERY_START was also a mess, with neither VIZQUERY_START nor HLSQ_FLUSH using variants. I added what seems like reasonable variants, based on the existing comment and the fact that HLSQ_FLUSH is only used in Mesa with a3xx and a4xx. - CACHE_FLUSH_AND_INVALIDATE seems to come straight from R600, and I have no idea if it's actually valid with a2xx, but given that RB_DONE_TS exists in the interrupt mask since a3xx, I guessed that RB_DONE_TS hasn't changed position since then and put it down as a3xx+ and limited CACHE_FLUSH_AND_INVALIDATE to a2xx. Someone with the relevant hardware should be able to confirm. Part-of: --- diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml index a2b69c57a12..c5d83d06550 100644 --- a/src/freedreno/registers/adreno_pm4.xml +++ b/src/freedreno/registers/adreno_pm4.xml @@ -11,9 +11,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> - - - + + + @@ -24,13 +24,15 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> - + + +