From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 8 Aug 2017 03:20:17 +0000 (-0700)
Subject: Fixed typo in last commit
X-Git-Tag: yosys-0.8~346^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3618ca22181715cd24f6dca5911019d406f562e7;p=yosys.git

Fixed typo in last commit
---

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 0b83b7a2c..250f1da6a 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -119,7 +119,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
 		if(UP)
-			OUT <= (count == 14'h4000);
+			OUT <= (count == 14'h3fff);
 		else
 			OUT <= (count == 14'h0);
 		POUT <= count[7:0];
@@ -144,7 +144,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 					//Wrapping
 					if(count == 0 && !UP)
 						count	<= COUNT_TO;
-					if(count == 14'h4000 && UP)
+					if(count == 14'h3fff && UP)
 						count	<= COUNT_TO;
 
 					//Resets
@@ -172,7 +172,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 					//Wrapping
 					if(count == 0 && !UP)
 						count	<= COUNT_TO;
-					if(count == 14'h4000 && UP)
+					if(count == 14'h3fff && UP)
 						count	<= COUNT_TO;
 
 					//Resets