From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 7 May 2020 19:54:32 +0000 (-0400)
Subject: Add test_branch_loop_ctr
X-Git-Tag: div_pipeline~1351
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3621fda3a857ffe25bfe56463266c9cac98673bd;p=soc.git

Add test_branch_loop_ctr
---

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 15a8997e..97499d49 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -154,7 +154,19 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program)
             # Verified with qemu
             self.assertEqual(sim.gpr(2), SelectableInt(0x37, 64))
-                    
+
+    def test_branch_loop_ctr(self):
+        lst = ["addi 1, 0, 0",
+               "addi 2, 0, 7",
+               "mtspr 9, 2",    # set ctr to 7
+               "addi 1, 1, 5",
+               "bc 16, 0, -0x4"]  # bdnz to the addi above
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            # Verified with qemu
+            self.assertEqual(sim.gpr(1), SelectableInt(0x23, 64))
+
+
 
     def test_add_compare(self):
         lst = ["addis 1, 0, 0xffff",