From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 20 Aug 2008 04:59:09 +0000 (-0700)
Subject: CPU: Get rid of two more duplicated CPU params.
X-Git-Tag: m5_2.0_beta6~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3633a916c299a1f5df9f6d34a0215cdae68a3e93;p=gem5.git

CPU: Get rid of two more duplicated CPU params.
---

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 87e8b5509..b7174bb43 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -35,8 +35,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index b7f044bfa..ce6839241 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -32,8 +32,6 @@ from BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']