From: lkcl <lkcl@web>
Date: Sat, 24 Sep 2022 23:14:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~308
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3639c1d4534901b9cbde7f1f7100d93e7005b258;p=libreriscv.git

---

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index 2c488eabb..a430af00a 100644
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -208,5 +208,7 @@ MSB0 numbering.  We start with some definitions:
 
 First we define the contents of 64-bit registers:
 
-    r0 : | b0 b1 b2 b3 b4 b5 b6 b7 | ... | b56 b57 b58 b59 b60 b61 b62 b63 |
-         |        B0               | ... |  B7                             |
+| name | hi      byte/bit        | ... | lo byte/bit                     |
+|------|-------------------------|-----|---------------------------------|
+| bits | b0 b1 b2 b3 b4 b5 b6 b7 | ... | b56 b57 b58 b59 b60 b61 b62 b63 |
+| bytes|        B0               | ... |  B7                             |