From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 14 Feb 2021 22:21:34 +0000 (-0300)
Subject: Fix width of the "extra" input on the Extra decoder
X-Git-Tag: convert-csv-opcode-to-binary~231^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=363c8694d37f52bf7de72852a38a53e70f8ac695;p=soc.git

Fix width of the "extra" input on the Extra decoder

The Extra field is nine bits long.
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index a1a69c99..9058b80f 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -87,7 +87,7 @@ class SVP64ExtraSpec(Elaboratable):
     see https://libre-soc.org/openpower/sv/svp64/
     """
     def __init__(self):
-        self.extra   = Signal(10, reset_less=True)
+        self.extra   = Signal(9, reset_less=True)
         self.etype   = Signal(SVEtype, reset_less=True) # 2 or 3 bits
         self.idx     = Signal(SVEXTRA, reset_less=True) # which part of extra
         self.spec  = Signal(3) # EXTRA spec for the register