From: lkcl <lkcl@web>
Date: Sat, 2 Jul 2022 21:30:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1405
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=363cb178cb690ba13cbaec239859867f64624f28;p=libreriscv.git

---

diff --git a/openpower/sv/vector_isa_comparison.mdwn b/openpower/sv/vector_isa_comparison.mdwn
index 6b6947f5d..1e3ce786d 100644
--- a/openpower/sv/vector_isa_comparison.mdwn
+++ b/openpower/sv/vector_isa_comparison.mdwn
@@ -53,8 +53,9 @@ of a Vector Processor. Transcendentals can be added as a sub-RFC.
 # SIMD ISAs commonly mistaken for Vector
 
 There is considerable confusion surrounding Vector ISAs
-because of a mis-use of the word "Vector" in most
-well-known Packed SIMD ISAs.
+because of a mis-use of the word "Vector" in the marketing
+material of most well-known Packed SIMD ISAs. These Packed
+SIMD ISAs used features "inspired" from Scalable Vector ISAs.
 
 * PackedSIMD VSX. VSX, which has the word "Vector" in its name,
   is "inspired" by Vector Processing