From: lkcl <lkcl@web>
Date: Mon, 21 Dec 2020 20:13:47 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1070
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=363e8bd8b0301888f1bf4a92c9403c53b35a3377;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index b2a70414f..807e6a4cd 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -17,7 +17,8 @@ Advantages of these design principles:
 * More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
 * As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance
 * Completely wipes not just SIMD opcode proliferation off the
-  map but off of Vectorisation ISAs as well.  No more separate Vector
+  map (SIMD is O(N^6) opcode proliferation)
+  but off of Vectorisation ISAs as well.  No more separate Vector
   instructions.
 
 Pages being developed and examples