From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 12 Jul 2013 11:13:04 +0000 (+0200)
Subject: More fixes in ternary op sign handling
X-Git-Tag: yosys-0.2.0~533
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3650fd7fbe45a00792770d9ecb9397bc27ea0845;p=yosys.git

More fixes in ternary op sign handling
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index a9574254d..e7ceec5f9 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -998,6 +998,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// generate multiplexer for ternary operator (aka ?:-operator)
 	case AST_TERNARY:
 		{
+			if (width_hint < 0)
+				detectSignWidth(width_hint, sign_hint);
+
 			RTLIL::SigSpec cond = children[0]->genRTLIL();
 			RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
 			RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index c97a2be50..fffa35050 100644
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -65,3 +65,11 @@ module test09(a, b, c, y);
   assign y = a ? b : c;
 endmodule
 
+module test10(a, b, c, y);
+  input a;
+  input signed [1:0] b;
+  input signed [2:0] c;
+  output y;
+  assign y = ^(a ? b : c);
+endmodule
+