From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Fri, 18 Oct 2019 23:34:48 +0000 (+1100)
Subject: simple_ram: Turn on pipelining
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=365f60b69391e193032d8b3bb961b2da707fd5c7;p=microwatt.git

simple_ram: Turn on pipelining

With a 1 cycle delay

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

diff --git a/simple_ram_behavioural.vhdl b/simple_ram_behavioural.vhdl
index 64135b8..d6255b8 100644
--- a/simple_ram_behavioural.vhdl
+++ b/simple_ram_behavioural.vhdl
@@ -11,7 +11,7 @@ entity mw_soc_memory is
     generic (
         RAM_INIT_FILE  : string;
         MEMORY_SIZE    : integer;
-	PIPELINE_DEPTH : integer := 0
+	PIPELINE_DEPTH : integer := 1
         );
 
     port (