From: Luke Kenneth Casson Leighton Date: Sat, 4 May 2019 07:28:58 +0000 (+0100) Subject: add FU-FU Dependency Matrix X-Git-Tag: ls180-24jan2020~1035 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36740df43088a8a8287fa9634a46d1529b0fa89c;p=ieee754fpu.git add FU-FU Dependency Matrix --- diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py new file mode 100644 index 00000000..6ffd4442 --- /dev/null +++ b/src/scoreboard/fu_fu_matrix.py @@ -0,0 +1,157 @@ +from nmigen.compat.sim import run_simulation +from nmigen.cli import verilog, rtlil +from nmigen import Module, Signal, Elaboratable, Array, Cat + +#from nmutil.latch import SRLatch +from fu_dep_cell import FUDependenceCell +from fu_picker_vec import FU_Pick_Vec + +""" + + 6600 Function Unit Dependency Table Matrix inputs / outputs + ----------------------------------------------------------- + +""" + +class FUFUDepMatrix(Elaboratable): + """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26 + """ + def __init__(self, n_fu_row, n_fu_col): + self.n_fu_row = n_fu_row # Y (FU row#) ^v + self.n_fu_col = n_fu_col # X (FU col #) <> + self.rd_pend_i = Signal(n_fu_row, reset_less=True) # Rd pending (left) + self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left) + self.issue_i = Signal(n_fu_col, reset_less=True) # Issue in (top) + + self.go_write_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) + self.go_read_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) + + # for Function Unit Readable/Writable (horizontal) + self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot) + self.writable_o = Signal(n_fu_col, reset_less=True) # writable (bot) + + def elaborate(self, platform): + m = Module() + + # --- + # matrix of dependency cells + # --- + dm = Array(Array(FUDependenceCell() for r in range(self.n_fu_row)) \ + for f in range(self.n_fu_col)) + for x in range(self.n_fu_col): + for y in range(self.n_fu_row): + setattr(m.submodules, "dm_fx%d_fy%d" % (x, y), dm[x][y]) + + # --- + # array of Function Unit Readable/Writable: row-length, horizontal + # --- + fur = Array(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col)) + for x in range(self.n_fu_col): + setattr(m.submodules, "fur_x%d" % (x), fur[x]) + + # --- + # connect FU Readable/Writable vector + # --- + readable = [] + writable = [] + for x in range(self.n_fu_col): + fu = fur[x] + rd_pend_o = [] + wr_pend_o = [] + for y in range(self.n_fu_row): + dc = dm[x][y] + # accumulate cell outputs rd/wr-pending + rd_pend_o.append(dc.rd_pend_o) + wr_pend_o.append(dc.wr_pend_o) + # connect cell reg-select outputs to Reg Vector In + m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_pend_o)), + fu.wr_pend_i.eq(Cat(*wr_pend_o)), + ] + # accumulate Readable/Writable Vector outputs + readable.append(fu.readable_o) + writable.append(fu.writable_o) + + # ... and output them from this module (horizontal, width=REGs) + m.d.comb += self.readable_o.eq(Cat(*readable)) + m.d.comb += self.writable_o.eq(Cat(*writable)) + + # --- + # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i + # --- + for y in range(self.n_fu_row): + issue_i = [] + for x in range(self.n_fu_col): + dc = dm[x][y] + # accumulate cell inputs issue + issue_i.append(dc.issue_i) + # wire up inputs from module to row cell inputs (Cat is gooood) + m.d.comb += Cat(*issue_i).eq(self.issue_i) + + # --- + # connect Matrix go_read_i/go_write_i to module readable/writable + # --- + for x in range(self.n_fu_col): + go_read_i = [] + go_write_i = [] + rd_pend_i = [] + wr_pend_i = [] + for y in range(self.n_fu_row): + dc = dm[x][y] + # accumulate cell rd_pend/wr_pend/go_read/go_write + rd_pend_i.append(dc.rd_pend_i) + wr_pend_i.append(dc.wr_pend_i) + go_read_i.append(dc.go_read_i) + go_write_i.append(dc.go_write_i) + # wire up inputs from module to row cell inputs (Cat is gooood) + m.d.comb += [Cat(*go_read_i).eq(self.go_read_i), + Cat(*go_write_i).eq(self.go_write_i), + Cat(*rd_pend_i).eq(self.rd_pend_i), + Cat(*wr_pend_i).eq(self.wr_pend_i), + ] + + return m + + def __iter__(self): + yield self.rd_pend_i + yield self.wr_pend_i + yield self.issue_i + yield self.go_write_i + yield self.go_read_i + yield self.readable_o + yield self.writable_o + + def ports(self): + return list(self) + +def d_matrix_sim(dut): + """ XXX TODO + """ + yield dut.dest_i.eq(1) + yield dut.issue_i.eq(1) + yield + yield dut.issue_i.eq(0) + yield + yield dut.src1_i.eq(1) + yield dut.issue_i.eq(1) + yield + yield dut.issue_i.eq(0) + yield + yield dut.go_read_i.eq(1) + yield + yield dut.go_read_i.eq(0) + yield + yield dut.go_write_i.eq(1) + yield + yield dut.go_write_i.eq(0) + yield + +def test_fu_fu_matrix(): + dut = FUFUDepMatrix(n_fu_row=3, n_fu_col=4) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_fu_fu_matrix.il", "w") as f: + f.write(vl) + + run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_fu_matrix.vcd') + +if __name__ == '__main__': + test_fu_fu_matrix() diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index c21cf34e..0826ea56 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -139,7 +139,6 @@ class FURegDepMatrix(Elaboratable): # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i # --- for rn in range(self.n_reg_col): - rsv = regrsv[rn] dest_i = [] src1_i = [] src2_i = [] @@ -162,7 +161,6 @@ class FURegDepMatrix(Elaboratable): # connect Dependency Matrix go_read_i/go_write_i to module go_rd/go_wr # --- for fu in range(self.n_fu_row): - fup = fupend[fu] go_read_i = [] go_write_i = [] for rn in range(self.n_reg_col):