From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Mar 2020 08:37:24 +0000 (+0000)
Subject: store ra in intermediate, to avoid creation of decoding twice
X-Git-Tag: div_pipeline~1722
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=367464777aca913050902af4dd799ba7414e7c26;p=soc.git

store ra in intermediate, to avoid creation of decoding twice
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 436005c6..8af57933 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -32,10 +32,12 @@ class DecodeA(Elaboratable):
         comb = m.d.comb
 
         # select Register A field
+        ra = Signal(5, reset_less=True)
+        comb += ra.eq(self.dec.RA[0:-1])
         with m.If((self.sel_in == In1Sel.RA) |
                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
-                   (self.dec.RA[0:-1] != Const(0, 5)))):
-            comb += self.reg_out.data.eq(self.dec.RA[0:-1])
+                   (ra != Const(0, 5)))):
+            comb += self.reg_out.data.eq(ra)
             comb += self.reg_out.ok.eq(1)
 
         # zero immediate requested