From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 27 Feb 2015 13:18:13 +0000 (+0100)
Subject: reserve csr_map 0-->16 for gensoc internal csrs
X-Git-Tag: 24jan2021_ls180~2587
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=367db268adfd8ef2bf769b64e5e2540e7b088c24;p=litex.git

reserve csr_map 0-->16 for gensoc internal csrs
---

diff --git a/targets/kc705.py b/targets/kc705.py
index 73505a85..6f278399 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -66,8 +66,8 @@ class BaseSoC(SDRAMSoC):
 	default_platform = "kc705"
 
 	csr_map = {
-		"spiflash":	10,
-		"ddrphy":	11,
+		"spiflash":	16,
+		"ddrphy":	17,
 	}
 	csr_map.update(SDRAMSoC.csr_map)
 
@@ -110,8 +110,8 @@ class BaseSoC(SDRAMSoC):
 
 class MiniSoC(BaseSoC):
 	csr_map = {
-		"ethphy":		12,
-		"ethmac":		13,
+		"ethphy":		18,
+		"ethmac":		19,
 	}
 	csr_map.update(BaseSoC.csr_map)
 
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index b30b86b2..dc4d58cb 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -74,8 +74,8 @@ PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
 
 class MiniSoC(BaseSoC):
 	csr_map = {
-		"ethphy":		10,
-		"ethmac":		11,
+		"ethphy":		16,
+		"ethmac":		17,
 	}
 	csr_map.update(BaseSoC.csr_map)
 
@@ -128,7 +128,7 @@ TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
 
 class FramebufferSoC(MiniSoC):
 	csr_map = {
-		"fb":					12,
+		"fb":					18,
 	}
 	csr_map.update(MiniSoC.csr_map)
 
diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 069ff48e..4d7673ec 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -67,7 +67,7 @@ class BaseSoC(SDRAMSoC):
 	default_platform = "pipistrello"
 
 	csr_map = {
-		"spiflash":	10,
+		"spiflash":	16,
 	}
 	csr_map.update(SDRAMSoC.csr_map)
 
diff --git a/targets/ppro.py b/targets/ppro.py
index 761edcb8..a6f59d32 100644
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -61,7 +61,7 @@ class BaseSoC(SDRAMSoC):
 	default_platform = "papilio_pro"
 
 	csr_map = {
-		"spiflash":	10,
+		"spiflash":	16,
 	}
 	csr_map.update(SDRAMSoC.csr_map)