From: Jędrzej Boczar <jboczar@antmicro.com>
Date: Wed, 22 Jul 2020 14:57:51 +0000 (+0200)
Subject: soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"
X-Git-Tag: 24jan2021_ls180~64^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=367eb1224094fea995ba19181b9e9fa3a1c56f75;p=litex.git

soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"
---

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 096ad055..2b3d3d03 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -766,8 +766,16 @@ class SoC(Module):
         self.csr.add(name, use_loc_if_exists=True)
 
     def add_ram(self, name, origin, size, contents=[], mode="rw"):
-        ram_bus = wishbone.Interface(data_width=self.bus.data_width)
-        ram     = wishbone.SRAM(size, bus=ram_bus, init=contents, read_only=(mode == "r"))
+        ram_cls = {
+            "wishbone": wishbone.SRAM,
+            "axi-lite": axi.AXILiteSRAM,
+        }[self.bus.standard]
+        interface_cls = {
+            "wishbone": wishbone.Interface,
+            "axi-lite": axi.AXILiteInterface,
+        }[self.bus.standard]
+        ram_bus = interface_cls(data_width=self.bus.data_width)
+        ram     = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"))
         self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
         self.check_if_exists(name)
         self.logger.info("RAM {} {} {}.".format(