From: Andrey Miroshnikov Date: Thu, 27 Apr 2023 15:33:10 +0000 (+0000) Subject: microwatt_tutorial: Added link to IRC logs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=369f0e830d977fe49781afef84ac943e0bb834ef;p=libreriscv.git microwatt_tutorial: Added link to IRC logs --- diff --git a/HDL_workflow/microwatt_tutorial.mdwn b/HDL_workflow/microwatt_tutorial.mdwn index 03cb94bcd..1f521567d 100644 --- a/HDL_workflow/microwatt_tutorial.mdwn +++ b/HDL_workflow/microwatt_tutorial.mdwn @@ -30,6 +30,7 @@ but somewhere else '.so' gets appended. You may see the following error if you don't redefine: `ERROR: Can't load module ./ghdl.so':/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`) +[IRC](https://libre-soc.org/irclog/%23libre-soc.2023-01-25.log.html#t2023-01-25T11:10:47) To run the Verilator simulation, set verilator as the target: