From: Gabe Black Date: Sat, 7 Jan 2012 10:10:34 +0000 (-0800) Subject: Merge with main repository. X-Git-Tag: stable_2012_06_28~278 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36a822f08e88483b41af214ace4fd3dccf3aa8cb;p=gem5.git Merge with main repository. --- 36a822f08e88483b41af214ace4fd3dccf3aa8cb diff --cc src/arch/alpha/ev5.cc index 9863a7370,6259f8fc2..4dcc58ffe --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@@ -255,10 -260,11 +253,9 @@@ ISA::setIpr(int idx, uint64_t val, Thre case IPR_PALtemp23: // write entire quad w/ no side-effect - old = ipr[idx]; - ipr[idx] = val; -#if FULL_SYSTEM if (tc->getKernelStats()) - tc->getKernelStats()->context(old, val, tc); + tc->getKernelStats()->context(ipr[idx], val, tc); -#endif + ipr[idx] = val; break; case IPR_DTB_PTE: diff --cc src/arch/sparc/isa/formats/mem/util.isa index d6eee8a4d,0ca56252e..a77059181 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@@ -326,8 -326,8 +326,8 @@@ let { ''' TruncateEA = ''' - if (!FullSystem) - EA = Pstate<3:> ? EA<31:0> : EA; - if (!FULL_SYSTEM) ++ if (!FullSystem) + EA = Pstate<3:> ? EA<31:0> : EA; ''' }}; diff --cc src/cpu/inorder/cpu.cc index 9d6ecc7e1,232554db2..010bdb512 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@@ -214,32 -218,33 +213,33 @@@ InOrderCPU::InOrderCPU(Params *params // Resize for Multithreading CPUs thread.resize(numThreads); -#if !FULL_SYSTEM + ThreadID active_threads = params->workload.size(); + if (FullSystem) { + active_threads = 1; + } else { + active_threads = params->workload.size(); - if (active_threads > MaxThreads) { - panic("Workload Size too large. Increase the 'MaxThreads'" - "in your InOrder implementation or " - "edit your workload size."); - } + if (active_threads > MaxThreads) { + panic("Workload Size too large. Increase the 'MaxThreads'" + "in your InOrder implementation or " + "edit your workload size."); + } - - if (active_threads > 1) { - threadModel = (InOrderCPU::ThreadModel) params->threadModel; - - if (threadModel == SMT) { - DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n"); - } else if (threadModel == SwitchOnCacheMiss) { - DPRINTF(InOrderCPU, "Setting Thread Model to " - "Switch On Cache Miss\n"); + + if (active_threads > 1) { + threadModel = (InOrderCPU::ThreadModel) params->threadModel; + + if (threadModel == SMT) { + DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n"); + } else if (threadModel == SwitchOnCacheMiss) { + DPRINTF(InOrderCPU, "Setting Thread Model to " + "Switch On Cache Miss\n"); + } + + } else { + threadModel = Single; } - - } else { - threadModel = Single; } - - - -#endif // Bind the fetch & data ports from the resource pool. fetchPortIdx = resPool->getPortIdx(params->fetchMemPort); diff --cc src/mem/page_table.cc index c260ba2d4,7622c2d48..0ec2dbc07 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@@ -215,13 -224,12 +224,13 @@@ PageTable::unserialize(Checkpoint *cp, pTable.clear(); - while(i < count) { + while (i < count) { + TheISA::TlbEntry *entry; + Addr vaddr; + - paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr); + paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr); entry = new TheISA::TlbEntry(); - entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i)); + entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); pTable[vaddr] = *entry; ++i; } diff --cc src/python/swig/pyobject.cc index 82a54545f,c8555cd31..3478310b1 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@@ -88,32 -94,28 +88,27 @@@ in connectPorts(SimObject *o1, const std::string &name1, int i1, SimObject *o2, const std::string &name2, int i2) { - MemObject *mo1, *mo2; - mo1 = dynamic_cast(o1); - mo2 = dynamic_cast(o2); -#if FULL_SYSTEM - EtherObject *eo1, *eo2; - EtherDevice *ed1, *ed2; - eo1 = dynamic_cast(o1); - ed1 = dynamic_cast(o1); -- - eo2 = dynamic_cast(o2); - ed2 = dynamic_cast(o2); + if (FullSystem) { + EtherObject *eo1, *eo2; + EtherDevice *ed1, *ed2; + eo1 = dynamic_cast(o1); + ed1 = dynamic_cast(o1); - + eo2 = dynamic_cast(o2); + ed2 = dynamic_cast(o2); - if ((eo1 || ed1) && (eo2 || ed2)) { - EtherInt *p1 = lookupEthPort(o1, name1, i1); - EtherInt *p2 = lookupEthPort(o2, name2, i2); + if ((eo1 || ed1) && (eo2 || ed2)) { + EtherInt *p1 = lookupEthPort(o1, name1, i1); + EtherInt *p2 = lookupEthPort(o2, name2, i2); - if (p1 != NULL && p2 != NULL) { + if (p1 != NULL && p2 != NULL) { - p1->setPeer(p2); - p2->setPeer(p1); + p1->setPeer(p2); + p2->setPeer(p1); - return 1; + return 1; + } } } -#endif Port *p1 = lookupPort(o1, name1, i1); Port *p2 = lookupPort(o2, name2, i2); diff --cc src/sim/system.cc index 654bcef80,c58830c10..3051cb64b --- a/src/sim/system.cc +++ b/src/sim/system.cc @@@ -260,11 -273,12 +260,11 @@@ System::replaceThreadContext(ThreadCont remoteGDB[context_id]->replaceThreadContext(tc); } -#if !FULL_SYSTEM Addr - System::new_page() + System::allocPhysPages(int npages) { Addr return_addr = pagePtr << LogVMPageSize; - ++pagePtr; + pagePtr += npages; if (return_addr >= physmem->size()) fatal("Out of memory, please increase size of physical memory."); return return_addr; diff --cc src/sim/system.hh index a8d336d03,ed5193dfd..00d8360e0 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@@ -271,8 -285,14 +271,10 @@@ class System : public SimObjec */ Addr getKernelEntry() const { return kernelEntry; } - Addr new_page(); -#else - + /// Allocate npages contiguous unused physical pages + /// @return Starting address of first page + Addr allocPhysPages(int npages); -#endif // FULL_SYSTEM - int registerThreadContext(ThreadContext *tc, int assigned=-1); void replaceThreadContext(ThreadContext *tc, int context_id);