From: Robert Ou <rqou@robertou.com>
Date: Mon, 26 Jun 2017 03:58:45 +0000 (-0700)
Subject: coolrunner2: Initial mapping of latches
X-Git-Tag: yosys-0.8~402^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36b75dfcb71329e378caa88f5390ef9a8598b674;p=yosys.git

coolrunner2: Initial mapping of latches
---

diff --git a/techlibs/coolrunner2/Makefile.inc b/techlibs/coolrunner2/Makefile.inc
index d1672e782..96bbb0f47 100644
--- a/techlibs/coolrunner2/Makefile.inc
+++ b/techlibs/coolrunner2/Makefile.inc
@@ -2,5 +2,6 @@
 OBJS += techlibs/coolrunner2/synth_coolrunner2.o
 OBJS += techlibs/coolrunner2/coolrunner2_sop.o
 
+$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
 $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
 $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))
diff --git a/techlibs/coolrunner2/cells_latch.v b/techlibs/coolrunner2/cells_latch.v
new file mode 100644
index 000000000..f1e19da3a
--- /dev/null
+++ b/techlibs/coolrunner2/cells_latch.v
@@ -0,0 +1,19 @@
+module $_DLATCH_P_(input E, input D, output Q);
+    LDCP _TECHMAP_REPLACE_ (
+        .D(D),
+        .G(E),
+        .Q(Q),
+        .PRE(1'b0),
+        .CLR(1'b0)
+        );
+endmodule
+
+module $_DLATCH_N_(input E, input D, output Q);
+    LDCP_N _TECHMAP_REPLACE_ (
+        .D(D),
+        .G(E),
+        .Q(Q),
+        .PRE(1'b0),
+        .CLR(1'b0)
+        );
+endmodule
diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index f9f990c22..90eb4eb16 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -94,3 +94,43 @@ module FDCP_N (C, PRE, CLR, D, Q);
             Q <= D;
     end
 endmodule
+
+module LDCP (G, PRE, CLR, D, Q);
+    parameter INIT = 0;
+
+    input G, PRE, CLR, D;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @* begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (G == 1)
+            Q <= D;
+        else if (PRE == 1)
+            Q <= 1;
+    end
+endmodule
+
+module LDCP_N (G, PRE, CLR, D, Q);
+    parameter INIT = 0;
+
+    input G, PRE, CLR, D;
+    output reg Q;
+
+    initial begin
+        Q <= INIT;
+    end
+
+    always @* begin
+        if (CLR == 1)
+            Q <= 0;
+        else if (G == 0)
+            Q <= D;
+        else if (PRE == 1)
+            Q <= 1;
+    end
+endmodule
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cpp b/techlibs/coolrunner2/synth_coolrunner2.cpp
index c58b52cdf..791bcffbe 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cpp
+++ b/techlibs/coolrunner2/synth_coolrunner2.cpp
@@ -145,6 +145,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 		{
 			run("opt -fast -full");
 			run("techmap");
+			run("techmap -map +/coolrunner2/cells_latch.v");
 			run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
 		}
 
@@ -160,6 +161,8 @@ struct SynthCoolrunner2Pass : public ScriptPass
 			run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
 			run("dffinit -ff FDCP Q INIT");
 			run("dffinit -ff FDCP_N Q INIT");
+			run("dffinit -ff LDCP Q INIT");
+			run("dffinit -ff LDCP_N Q INIT");
 			run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
 		}