From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Apr 2020 03:56:38 +0000 (-0700)
Subject: techmap: sort celltypeMap as it determines techmap order
X-Git-Tag: working-ls180~517^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36bb201dd9572f71c74d0987d8f42b19a6feaa9c;p=yosys.git

techmap: sort celltypeMap as it determines techmap order
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 16bc9c803..8a8756757 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1313,11 +1313,13 @@ struct TechmapPass : public Pass {
 					celltypeMap[RTLIL::escape_id(q)].insert(module->name);
 				free(p);
 			} else {
-				std::string module_name = module->name.begins_with("\\$") ?
+				IdString module_name = module->name.begins_with("\\$") ?
 						module->name.substr(1) : module->name.str();
 				celltypeMap[module_name].insert(module->name);
 			}
 		}
+		for (auto &i : celltypeMap)
+			i.second.sort(RTLIL::sort_by_id_str());
 
 		for (auto module : design->modules())
 			worker.module_queue.insert(module);
@@ -1389,6 +1391,8 @@ struct FlattenPass : public Pass {
 		dict<IdString, pool<IdString>> celltypeMap;
 		for (auto module : design->modules())
 			celltypeMap[module->name].insert(module->name);
+		for (auto &i : celltypeMap)
+			i.second.sort(RTLIL::sort_by_id_str());
 
 		RTLIL::Module *top_mod = nullptr;
 		if (design->full_selection())