From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 25 Jul 2013 12:00:16 +0000 (+0200)
Subject: Added RTLIL and Liberty syntax highlighting to manual
X-Git-Tag: yosys-0.2.0~527
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36c39cbd04c760a833cb746ac5c71d667d9c87a7;p=yosys.git

Added RTLIL and Liberty syntax highlighting to manual
---

diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 40deabfac..f79f5f105 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -300,7 +300,7 @@ In this example there is no data path and therefore the RTLIL::Module generated
 the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process.
 The RTLIL::Process in ILANG syntax:
 
-\begin{lstlisting}[numbers=left,frame=single]
+\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
 process $proc$ff_with_en_and_async_reset.v:4$1
 	assign $0\q[0:0] \q
 	switch \reset
@@ -364,7 +364,7 @@ One of the first actions performed on a design in RTLIL representation in most
 synthesis scripts is identifying asynchronous resets. This is usually done using the {\tt proc\_arst}
 pass. This pass transforms the above example to the following RTLIL::Process:
 
-\begin{lstlisting}[numbers=left,frame=single]
+\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
 process $proc$ff_with_en_and_async_reset.v:4$1
 	assign $0\q[0:0] \q
 	switch \enable
@@ -383,7 +383,7 @@ This pass has transformed the outer RTLIL::SwitchRule into a modified RTLIL::Syn
 for the {\tt \textbackslash{}reset} signal. Further processing converts the RTLIL::Process
 e.g.~into a d-type flip-flop with asynchronous reset and a multiplexer for the enable signal:
 
-\begin{lstlisting}[numbers=left,frame=single]
+\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
 cell $adff $procdff$6
 	parameter \ARST_POLARITY 1'1
 	parameter \ARST_VALUE 1'0
diff --git a/manual/CHAPTER_Verilog.tex b/manual/CHAPTER_Verilog.tex
index 80f55a258..960747747 100644
--- a/manual/CHAPTER_Verilog.tex
+++ b/manual/CHAPTER_Verilog.tex
@@ -533,7 +533,7 @@ end
 This is translated by the Verilog and AST frontends into the following RTLIL code (attributes, cell parameters
 and wire declarations not included):
 
-\begin{lstlisting}[numbers=left,frame=single]
+\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
 cell $logic_not $logic_not$<input>:4$2
   connect \A \in1
   connect \Y $logic_not$<input>:4$2_Y
diff --git a/manual/manual.tex b/manual/manual.tex
index 857c54abc..78c3b685e 100644
--- a/manual/manual.tex
+++ b/manual/manual.tex
@@ -102,6 +102,21 @@ bookmarksopen=false%
 \setlength{\parskip}{1.5ex plus 1ex minus 0.5ex}
 \setlength{\parindent}{0pt}
 
+\lstdefinelanguage{liberty}{
+	morecomment=[s]{/*}{*/},
+	morekeywords={library,cell,area,pin,direction,function,clocked_on,next_state,clock,ff},
+	morestring=[b]",
+}
+
+\lstdefinelanguage{rtlil}{
+	morecomment=[l]{//},
+	morecomment=[s]{/*}{*/},
+	morekeywords={module,attribute,parameter,wire,memory,auto,width,offset,size,input,output,inout,cell,connect,switch,case,assign,sync,low,high,posedge,negedge,edge,always,update,process,end},
+	morestring=[b]",
+}
+
+
+
 \begin{document}
 
 \fancypagestyle{mypagestyle}{%