From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 16:51:43 +0000 (-0700)
Subject: Fix more potential for undefined behaviour due to container invalidation
X-Git-Tag: working-ls180~1237^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36e2eb06bb63714d852b758062471222022930c3;p=yosys.git

Fix more potential for undefined behaviour due to container invalidation
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ae690ec49..d373ca77e 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -436,14 +436,18 @@ struct XAigerWriter
 					new_wire = module->addWire(wire_name, GetSize(wire));
 				SigBit new_bit(new_wire, bit.offset);
 				module->connect(new_bit, bit);
-				if (not_map.count(bit))
-					not_map[new_bit] = not_map.at(bit);
+				if (not_map.count(bit)) {
+					auto a = not_map.at(bit);
+					not_map[new_bit] = a;
+				}
 				else if (and_map.count(bit)) {
-				    //and_map[new_bit] = and_map.at(bit); // Breaks gcc-4.8
-				    and_map.insert(std::make_pair(new_bit, and_map.at(bit)));
+					auto a = and_map.at(bit);
+					and_map[new_bit] = a;
+				}
+				else if (alias_map.count(bit)) {
+					auto a = alias_map.at(bit);
+					alias_map[new_bit] = a;
 				}
-				else if (alias_map.count(bit))
-					alias_map[new_bit] = alias_map.at(bit);
 				else
 					alias_map[new_bit] = bit;
 				output_bits.erase(bit);