From: Tiago Muck Date: Wed, 20 Feb 2019 00:01:44 +0000 (-0600) Subject: mem-ruby: Cache latencies for MOESI_CMP_dir X-Git-Tag: v19.0.0.0~844 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36e49e2b5bd96d527596707b794fc5f57785c801;p=gem5.git mem-ruby: Cache latencies for MOESI_CMP_dir Modified both L1 and L2 controllers to take into account the cache latency parameters. Default values in the configuration script updated as well. Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979 Signed-off-by: Tiago Muck Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414 Tested-by: kokoro Reviewed-by: Nikos Nikoleris Maintainer: Jason Lowe-Power --- diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py index e3385fa77..18e9ef6c8 100644 --- a/configs/ruby/MOESI_CMP_directory.py +++ b/configs/ruby/MOESI_CMP_directory.py @@ -49,8 +49,13 @@ from Ruby import send_evicts # # Declare caches used by the protocol # -class L1Cache(RubyCache): pass -class L2Cache(RubyCache): pass +class L1Cache(RubyCache): + dataAccessLatency = 1 + tagAccessLatency = 1 + +class L2Cache(RubyCache): + dataAccessLatency = 20 + tagAccessLatency = 20 def define_options(parser): return diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 9bba73911..7503fb3d1 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -42,7 +42,8 @@ machine(MachineType:L1Cache, "L1 cache protocol") : Sequencer * sequencer; CacheMemory * L1Icache; CacheMemory * L1Dcache; - Cycles request_latency := 2; + Cycles request_latency := 1; + Cycles response_latency := 1; Cycles use_timeout_latency := 50; bool send_evictions; @@ -182,6 +183,24 @@ machine(MachineType:L1Cache, "L1 cache protocol") return State:I; } + // L1 hit latency + Cycles mandatoryQueueLatency(RubyRequestType type) { + if (type == RubyRequestType:IFETCH) { + return L1Icache.getTagLatency(); + } else { + return L1Dcache.getTagLatency(); + } + } + + // Latency for responses that fetch data from cache + Cycles cacheResponseLatency() { + if (L1Dcache.getTagLatency() > response_latency) { + return L1Dcache.getTagLatency(); + } else { + return response_latency; + } + } + void setState(TBE tbe, Entry cache_entry, Addr addr, State state) { assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false); @@ -510,7 +529,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") peek(requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); if (in_msg.RequestorMachine == MachineType:L2Cache) { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -526,7 +545,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") DPRINTF(RubySlicc, "Sending data to L2: %#x\n", in_msg.addr); } else { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -544,7 +563,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") } action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { assert(is_valid(cache_entry)); out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -563,7 +582,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") peek(requestNetwork_in, RequestMsg) { assert(is_valid(cache_entry)); if (in_msg.RequestorMachine == MachineType:L2Cache) { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -578,7 +597,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") DPRINTF(RubySlicc, "Sending exclusive data to L2\n"); } else { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -597,7 +616,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") action(f_sendAck, "f", desc="Send ack from cache to requestor") { peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L1Cache) { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -608,7 +627,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") } } else { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -623,7 +642,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") } action(g_sendUnblock, "g", desc="Send unblock to memory") { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; @@ -635,7 +654,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") } action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Sender := machineID; @@ -746,7 +765,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") { peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DMA_ACK; out_msg.Sender := machineID; @@ -765,7 +784,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") assert(is_valid(tbe)); if (in_msg.RequestorMachine == MachineType:L1Cache || in_msg.RequestorMachine == MachineType:DMA) { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -779,7 +798,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") } } else { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -800,7 +819,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") peek(requestNetwork_in, RequestMsg) { assert(is_valid(tbe)); if (in_msg.RequestorMachine == MachineType:L1Cache) { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -813,7 +832,7 @@ machine(MachineType:L1Cache, "L1 cache protocol") } } else { - enqueue(responseNetwork_out, ResponseMsg, request_latency) { + enqueue(responseNetwork_out, ResponseMsg, response_latency) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index 53b5a948f..7883a96b2 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -40,8 +40,8 @@ machine(MachineType:L2Cache, "Token protocol") : CacheMemory * L2cache; - Cycles response_latency := 2; - Cycles request_latency := 2; + Cycles response_latency := 1; + Cycles request_latency := 1; // L2 BANK QUEUES // From local bank of L2 cache TO the network @@ -248,6 +248,16 @@ machine(MachineType:L2Cache, "Token protocol") MachineID mapAddressToMachine(Addr addr, MachineType mtype); void wakeUpAllBuffers(Addr a); + // Latency for responses that fetch data from cache + Cycles cacheResponseLatency() { + if (L2cache.getTagLatency() > response_latency) { + return L2cache.getTagLatency(); + } + else { + return response_latency; + } + } + Entry getCacheEntry(Addr address), return_by_pointer="yes" { return static_cast(Entry, "pointer", L2cache[address]); } @@ -921,7 +931,7 @@ machine(MachineType:L2Cache, "Token protocol") action(d_sendDataToL1GETS, "d", desc="Send data directly to L1 requestor") { assert(is_valid(cache_entry)); peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -941,7 +951,7 @@ machine(MachineType:L2Cache, "Token protocol") action(d_sendDataToL1GETX, "\d", desc="Send data and a token from TBE to L1 requestor") { assert(is_valid(cache_entry)); peek(L1requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { assert(is_valid(tbe)); out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -961,7 +971,7 @@ machine(MachineType:L2Cache, "Token protocol") action(dd_sendDataToFwdGETX, "dd", desc="send data") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; @@ -981,7 +991,7 @@ machine(MachineType:L2Cache, "Token protocol") action(dd_sendDataToFwdGETS, "\dd", desc="send data") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; @@ -1001,7 +1011,7 @@ machine(MachineType:L2Cache, "Token protocol") action(dd_sendExclusiveDataToFwdGETS, "\d\d", desc="send data") { assert(is_valid(cache_entry)); peek(requestNetwork_in, RequestMsg) { - enqueue(responseNetwork_out, ResponseMsg, response_latency) { + enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID;