From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 18:26:44 +0000 (-0700)
Subject: Capitalisation
X-Git-Tag: yosys-0.9~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36f3cc9dcc07fc8a0c718fa0611ec39fd267900b;p=yosys.git

Capitalisation
---

diff --git a/CHANGELOG b/CHANGELOG
index 6931c3de0..6f476a2cb 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -47,7 +47,7 @@ Yosys 0.7 .. Yosys 0.8
     - Added Verilog $rtoi and $itor support
     - Added "check -initdrv"
     - Added "read_blif -wideports"
-    - Added support for systemVerilog "++" and "--" operators
+    - Added support for SystemVerilog "++" and "--" operators
     - Added support for SystemVerilog unique, unique0, and priority case
     - Added "write_edif" options for edif "flavors"
     - Added support for resetall compiler directive