From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Mar 2022 20:18:53 +0000 (+0000)
Subject: rename PLRU modules to avoid conflict in microwatt
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36f8a92eb6e900f69a375d793602b9353c32a540;p=soc.git

rename PLRU modules to avoid conflict in microwatt
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 917e9818..f2e4360a 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -847,7 +847,7 @@ class DCache(Elaboratable, DCacheConfig):
             return
 
         # suite of PLRUs with a selection and output mechanism
-        tlb_plrus = PLRUs(self.TLB_SET_SIZE, self.TLB_WAY_BITS)
+        tlb_plrus = PLRUs("d_tlb", self.TLB_SET_SIZE, self.TLB_WAY_BITS)
         m.submodules.tlb_plrus = tlb_plrus
         comb += tlb_plrus.way.eq(r1.tlb_hit.way)
         comb += tlb_plrus.valid.eq(r1.tlb_hit.valid)
@@ -953,7 +953,8 @@ class DCache(Elaboratable, DCacheConfig):
             return
 
         # suite of PLRUs with a selection and output mechanism
-        m.submodules.plrus = plrus = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plrus = PLRUs("dtag", self.NUM_LINES,
+                                                   self.WAY_BITS)
         comb += plrus.way.eq(r1.hit_way)
         comb += plrus.valid.eq(r1.cache_hit)
         comb += plrus.index.eq(r1.hit_index)
diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 5523c50c..e9c8ed1b 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -419,7 +419,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             return
 
 
-        m.submodules.plrus = plru = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plru = PLRUs("itag", self.NUM_LINES,
+                                                  self.WAY_BITS)
         comb += plru.way.eq(r.hit_way)
         comb += plru.valid.eq(r.hit_valid)
         comb += plru.index.eq(self.get_index(r.hit_nia))
diff --git a/src/soc/experiment/plru.py b/src/soc/experiment/plru.py
index 92b8fc14..661b784d 100644
--- a/src/soc/experiment/plru.py
+++ b/src/soc/experiment/plru.py
@@ -55,7 +55,8 @@ class PLRU(Elaboratable):
 
 
 class PLRUs(Elaboratable):
-    def __init__(self, n_plrus, n_bits):
+    def __init__(self, cachetype, n_plrus, n_bits):
+        self.cachetype = cachetype
         self.n_plrus = n_plrus
         self.n_bits = n_bits
         self.valid = Signal()
@@ -83,7 +84,8 @@ class PLRUs(Elaboratable):
 
         for i in range(self.n_plrus):
             # PLRU interface
-            m.submodules["plru_%d" % i] = plru = PLRU(self.n_bits)
+            name = "%s_plru_%d" % (self.cachetype, i)
+            m.submodules[name] = plru = PLRU(self.n_bits)
 
             comb += plru.acc_en.eq(te.o[i])
             comb += plru.acc_i.eq(self.way)
@@ -105,7 +107,7 @@ if __name__ == '__main__':
         f.write(vl)
 
 
-    dut = PLRUs(4, 2)
+    dut = PLRUs("testing", 4, 2)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_plrus.il", "w") as f:
         f.write(vl)