From: lkcl Date: Sun, 15 May 2022 20:56:55 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2215 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36f9763bef4187b2955562261255dbd5d9b98ae6;p=libreriscv.git --- diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 2a1421988..cf672e4a6 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -92,20 +92,20 @@ ternlog has its own major opcode TODO: convert all instructions to use RT and not RS -| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name | -| -- | -- | --- | --- | ----- | -------- |--| ------ | -| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | -| NN | | | | | 00 |1 | rsvd | -| NN | RT | RA | RB | im0-4 | im5-7 01 |0 | grevlog | -| NN | RT | RA | RB | im0-4 | im5-7 01 |1 | grevlogw | -| NN | RT | RA | RB | RC | mode 010 |Rc| bitmask\* | -| NN | RT | RA | RB | RC | 00 011 |nh| binlut | -| NN | | | | | 01 011 |0 | svshape | -| NN | | | | | 01 011 |1 | svremap | -| NN | | | | | 10 011 |Rc| svstep | -| NN | | | | | 11 011 |Rc| setvl | -| NN | | | | | ---- 110 | | 1/2 ops | -| NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi | +| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name | Form | +| -- | -- | --- | --- | ----- | -------- |--| ------ | -------- | +| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | | +| NN | | | | | 00 |1 | rsvd | | +| NN | RT | RA | RB | im0-4 | im5-7 01 |0 | grevlog | | +| NN | RT | RA | RB | im0-4 | im5-7 01 |1 | grevlogw | | +| NN | RT | RA | RB | RC | mode 010 |Rc| bitmask\* | | +| NN | RT | RA | RB | RC | 00 011 |nh| binlut | | +| NN | | | | | 01 011 |0 | svshape | | +| NN | | | | | 01 011 |1 | svremap | | +| NN | | | | | 10 011 |Rc| svstep | | +| NN | | | | | 11 011 |Rc| setvl | | +| NN | | | | | ---- 110 | | 1/2 ops | other table | +| NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi | | ops (note that av avg and abs as well as vec scalar mask are included here [[sv/vector_ops]], and