From: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri, 28 Sep 2018 10:39:10 +0000 (+0200)
Subject: iris: ...and SO prims emitted queries
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=36fbcfb06c7e733a42fc8f9444faa81631ae2852;p=mesa.git

iris: ...and SO prims emitted queries

looks like we have queries

some fails still due to races between snapshots_written and start/end
not being garbage...not sure what that's about
---

diff --git a/src/gallium/drivers/iris/iris_query.c b/src/gallium/drivers/iris/iris_query.c
index 4d6fda816b7..46006d493c7 100644
--- a/src/gallium/drivers/iris/iris_query.c
+++ b/src/gallium/drivers/iris/iris_query.c
@@ -172,6 +172,12 @@ write_value(struct iris_context *ice, struct iris_query *q, unsigned offset)
    struct iris_batch *batch = &ice->render_batch;
    const struct gen_device_info *devinfo = &batch->screen->devinfo;
 
+   if (!iris_is_query_pipelined(q)) {
+      iris_emit_pipe_control_flush(batch,
+                                   PIPE_CONTROL_CS_STALL |
+                                   PIPE_CONTROL_STALL_AT_SCOREBOARD);
+   }
+
    switch (q->type) {
    case PIPE_QUERY_OCCLUSION_COUNTER:
    case PIPE_QUERY_OCCLUSION_PREDICATE:
@@ -196,14 +202,16 @@ write_value(struct iris_context *ice, struct iris_query *q, unsigned offset)
                            offset);
       break;
    case PIPE_QUERY_PRIMITIVES_GENERATED:
-      iris_emit_pipe_control_flush(batch,
-                                   PIPE_CONTROL_CS_STALL |
-                                   PIPE_CONTROL_STALL_AT_SCOREBOARD);
       ice->vtbl.store_register_mem64(batch,
                                      q->index == 0 ? CL_INVOCATION_COUNT :
                                      SO_PRIM_STORAGE_NEEDED(q->index),
                                      q->bo, offset, false);
       break;
+   case PIPE_QUERY_PRIMITIVES_EMITTED:
+      ice->vtbl.store_register_mem64(batch,
+                                     SO_NUM_PRIMS_WRITTEN(q->index),
+                                     q->bo, offset, false);
+      break;
    case PIPE_QUERY_PIPELINE_STATISTICS: {
       static const uint32_t index_to_reg[] = {
          IA_VERTICES_COUNT,
@@ -220,10 +228,6 @@ write_value(struct iris_context *ice, struct iris_query *q, unsigned offset)
       };
       const uint32_t reg = index_to_reg[q->index];
 
-      iris_emit_pipe_control_flush(batch,
-                                   PIPE_CONTROL_CS_STALL |
-                                   PIPE_CONTROL_STALL_AT_SCOREBOARD);
-
       ice->vtbl.store_register_mem64(batch, reg, q->bo, offset, false);
       break;
    }