From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 23 Sep 2022 22:15:23 +0000 (+0100)
Subject: grr annoying recurrence of svshape bug, mscale starts with 6 bits
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=371c82cf6474dd3b4fbd5c900bae3ce92f60f958;p=openpower-isa.git

grr annoying recurrence of svshape bug, mscale starts with 6 bits
---

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 3a8387c0..e2b68ab3 100644
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -105,7 +105,7 @@ Pseudo-code:
 
     # for convenience, VL to be calculated and stored in SVSTATE
     vlen <- [0] * 7
-    mscale[0:6] <- 0b0000001 # for scaling MAXVL
+    mscale[0:5] <- 0b000001 # for scaling MAXVL
     itercount[0:6] <- [0] * 7
     SVSTATE[0:31] <- [0] * 32
     # only overwrite REMAP if "persistence" is zero