From: Michael Meissner Date: Fri, 23 Jun 2017 18:25:10 +0000 (+0000) Subject: re PR target/80510 (Optimize Power7/power8 Altivec load/stores) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37416b699f362c378a0351c3b2b2e32754a1cc76;p=gcc.git re PR target/80510 (Optimize Power7/power8 Altivec load/stores) [gcc] 2017-06-23 Michael Meissner PR target/80510 * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in 32-bit, since indexed is not valid for DImode. (mov_hardfloat32): Reorder ISA 2.07 load/stores before ISA 3.0 d-form load/stores to be the same as mov_hardfloat64. (define_peephole2 for Altivec d-form load): Add 32-bit support. (define_peephole2 for Altivec d-form store): Likewise. [gcc/testsuite] 2017-06-23 Michael Meissner PR target/80510 * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit. * gcc.target/powerpc/pr80510-2.c: Likewise. From-SVN: r249607 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3e43b44dddb..5019018802d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-06-23 Michael Meissner + PR target/80510 + * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in + 32-bit, since indexed is not valid for DImode. + (mov_hardfloat32): Reorder ISA 2.07 load/stores before ISA + 3.0 d-form load/stores to be the same as mov_hardfloat64. + (define_peephole2 for Altivec d-form load): Add 32-bit support. + (define_peephole2 for Altivec d-form store): Likewise. + PR ipa/81185 * multiple_target.c (create_dispatcher_calls): Only create the dispatcher call if the function is the default clone of a diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8e1b460ee81..f78dbf913ec 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -690,7 +690,9 @@ ;; Iterator to optimize the following cases: ;; D-form load to FPR register & move to Altivec register ;; Move Altivec register to FPR register and store -(define_mode_iterator ALTIVEC_DFORM [DI DF SF]) +(define_mode_iterator ALTIVEC_DFORM [DF + SF + (DI "TARGET_POWERPC64")]) ;; Start with fixed-point load and store insns. Here we put only the more @@ -7391,8 +7393,8 @@ ;; except for 0.0 which can be created on VSX with an xor instruction. (define_insn "*mov_hardfloat32" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,Z,,wY,,,!r,Y,r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,wY,,,,,r,Y,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,wY,,Z,,,!r,Y,r,!r") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,,Z,,,,,r,Y,r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7400,10 +7402,10 @@ stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 - lxsd%U1x %x0,%y1 - stxsd%U0x %x1,%y0 lxsd %0,%1 stxsd %1,%0 + lxsd%U1x %x0,%y1 + stxsd%U0x %x1,%y0 xxlor %x0,%x1,%x1 xxlxor %x0,%x0,%x0 # @@ -13967,13 +13969,13 @@ ;; LXSDX 32,3,9 (define_peephole2 - [(match_scratch:DI 0 "b") + [(match_scratch:P 0 "b") (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand") (match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand")) (set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand") (match_dup 1))] - "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_ - && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])" + "TARGET_VSX && TARGET_UPPER_REGS_ && !TARGET_P9_DFORM_SCALAR + && peep2_reg_dead_p (2, operands[1])" [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) @@ -13988,7 +13990,7 @@ add_op0 = XEXP (addr, 0); add_op1 = XEXP (addr, 1); gcc_assert (REG_P (add_op0)); - new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg); + new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg); operands[4] = add_op1; operands[5] = change_address (mem, mode, new_addr); @@ -14004,13 +14006,13 @@ ;; STXSDX 32,3,9 (define_peephole2 - [(match_scratch:DI 0 "b") + [(match_scratch:P 0 "b") (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand") (match_operand:ALTIVEC_DFORM 2 "altivec_register_operand")) (set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand") (match_dup 1))] - "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_ - && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])" + "TARGET_VSX && TARGET_UPPER_REGS_ && !TARGET_P9_DFORM_SCALAR + && peep2_reg_dead_p (2, operands[1])" [(set (match_dup 0) (match_dup 4)) (set (match_dup 5) @@ -14025,7 +14027,7 @@ add_op0 = XEXP (addr, 0); add_op1 = XEXP (addr, 1); gcc_assert (REG_P (add_op0)); - new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg); + new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg); operands[4] = add_op1; operands[5] = change_address (mem, mode, new_addr); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8c558622f78..a2694780368 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-23 Michael Meissner + + PR target/80510 + * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit. + * gcc.target/powerpc/pr80510-2.c: Likewise. + 2017-06-22 Jeff Law * gcc.c-torture/compile/stack-check-1.c: Require "untyped_assembly". diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c index d832e927b9f..deb51ac9916 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ @@ -6,9 +6,7 @@ /* Make sure that STXSDX is generated for double scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. - - 32-bit currently does not have support for STXSDX in the mov{df,dd} patterns. */ + store. */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c index 83a186bedc8..b4d2491551b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ @@ -6,9 +6,7 @@ /* Make sure that STXSSPX is generated for float scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. - - 32-bit currently does not have support for STXSSPX in the mov{sf,sd} patterns. */ + store. */ #ifndef TYPE #define TYPE float