From: Tobias Platen <tplaten@posteo.de>
Date: Wed, 3 Nov 2021 16:54:12 +0000 (+0100)
Subject: add first tlbie test case
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=374708df846afca556bfb6a284f5b256fc6f0349;p=soc.git

add first tlbie test case
---

diff --git a/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py b/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
index 47243b66..3e418091 100644
--- a/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
+++ b/src/soc/experiment/test/test_compldst_multi_mmu_fsm.py
@@ -40,6 +40,17 @@ from openpower.decoder.power_fieldsn import SignalBitRange
 from openpower.decoder.power_decoder2 import decode_spr_num
 from openpower.decoder.power_enums import MicrOp
 
+def test_TLBIE(dut):
+    yield dut.fsm.p.i_data.ctx.op.eq(MicrOp.OP_TLBIE)
+    yield dut.fsm.p.valid_i.eq(1)
+    yield
+    yield dut.fsm.p.valid_i.eq(0)
+    yield
+    yield
+    yield
+    yield
+    yield Display("OP_TLBIE test done")
+
 def ldst_sim(dut):
     yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
     addr = 0x100e0
@@ -52,13 +63,8 @@ def ldst_sim(dut):
     print(data,data_ok,ld_addr)
     assert(ld_data==data)
     yield
+    yield from test_TLBIE(dut)
 
-    ##### not yet complete
-    yield dut.fsm.p.i_data.ctx.op.eq(MicrOp.OP_TLBIE)
-    yield
-    yield
-    yield
-    yield
 
     """
     -- not testing dzbz here --
diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 7be930cc..036be0f4 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -24,7 +24,7 @@ from soc.experiment.mem_types import LoadStore1ToMMUType
 from soc.experiment.mem_types import MMUToLoadStore1Type
 
 from soc.fu.ldst.loadstore import LoadStore1, TestSRAMLoadStore1
-
+from nmutil.util import Display
 
 class FSMMMUStage(ControlBase):
     """FSM MMU
@@ -206,6 +206,7 @@ class FSMMMUStage(ControlBase):
                     # note that the spr is *not* an actual spr number, it's
                     # just that those bits happen to match with field bits
                     # RIC, PRS, R
+                    comb += Display("TLBIE: %i %i",spr,l_out.done)
                     comb += valid.eq(1)   # start "pulse"
                     comb += l_in.valid.eq(blip)   # start
                     comb += l_in.tlbie.eq(1)   # mtspr mode