From: lkcl <lkcl@web>
Date: Mon, 12 Sep 2022 15:33:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~467
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3755f7f7ca121c2cd13a81bad29383180f25e68e;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 1d2fa4ae5..a5a271aae 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -49,12 +49,10 @@ The Mode table for Arithmetic and Logical operations
 | 00  |   0 |  dz  sz | simple mode                      |
 | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
 | 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
-| 00  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
+| 00  |   1 | /   1   | reserved   |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
-| 10  |   N | dz   sz |  sat mode: N=0/1 u/s, SUBVL=1 |
-| 10  |   N | zz   0  |  sat mode: N=0/1 u/s, SUBVL>1 |
-| 10  |   N | zz   1  |  Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1 |
+| 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 | 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
 
@@ -118,10 +116,6 @@ new crrweird instruction with Rc=1, which will transfer the required
 CR bits to a scalar integer and update CR0, which will allow testing
 the scalar integer for nonzero.  see [[sv/cr_int_predication]]*
 
-Pack/Unpack may be enabled at the same time as Saturation,
-when SUBVL is vec2/3/4. This provides equivalent VSX `vpkpx` and other
-operations.
-
 # Reduce mode
 
 Reduction in SVP64 is similar in essence to other Vector Processing
@@ -269,6 +263,8 @@ different: elements that fail the CR test *or* are masked out are zero'd.
 
 # Pack/Unpack Mode
 
+TODO - move to `sv.setvl` [[sv/setvl]]
+
 Structured Pack/Unpack is similar to VSX `vpack` and `vunpack` except
 generalised not only to a Schedule to be applied to any operation but
 also extended to vec2/3/4.