From: whitequark <whitequark@whitequark.org>
Date: Tue, 2 Mar 2021 06:46:07 +0000 (-0800)
Subject: Merge pull request #2620 from zachjs/port-int-types
X-Git-Tag: working-ls180~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=375af199ef4df45ccf02c66e0171b4282c6cf1eb;p=yosys.git

Merge pull request #2620 from zachjs/port-int-types

verilog: fix sizing of ports with int types in module headers
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375af199ef4df45ccf02c66e0171b4282c6cf1eb