From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 25 Sep 2019 08:18:57 +0000 (+0100)
Subject: add link to appendix and mention use of tpred mode for branch on SVP
X-Git-Tag: convert-csv-opcode-to-binary~3971
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37652972a75d7cd7c86de8743a172babe3a44ad3;p=libreriscv.git

add link to appendix and mention use of tpred mode for branch on SVP
---

diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index ebf3f5ac1..6e67b1ca3 100644
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -12,6 +12,7 @@ into 32, 48 and 64 bit RV formats, to provide Vectorisation context
 on a per-instruction basis.
 
 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
+.. _Appendix: http://libre-riscv.org/simple_v_extension/appendix/
 
 .. contents::
 
@@ -434,6 +435,13 @@ Predication (pred) Field Encoding
 Twin-predication (tpred) Field Encoding
 =======================================
 
+Twin-predication (ability to associate two predicate registers with an
+instruction) applies to MV, FCLASS, LD and ST.  The same format also
+applies to integer-branch-compare operations although it is **not** to be
+considered "twin" predication.  In the case of integer-branch-compare
+operations, the second register (if enabled) stores the results of the
+element comparisons.  See Appendix_ for details.
+
 +-------+------------+--------------------+----------------------------------------------+
 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 +=======+============+====================+==============================================+