From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 2 May 2021 14:38:37 +0000 (+0100)
Subject: return d_out.valid instead of always "ok" in MMU FSM
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3769d716314a784393253c3d735f9b54ec1af9bb;p=soc.git

return d_out.valid instead of always "ok" in MMU FSM
---

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index aeffb5c2..abcc06cf 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -76,8 +76,8 @@ class LoadStore1(PortInterfaceBase):
 
     def set_wr_data(self, m, data, wen):
         m.d.sync += self.d_in.data.eq(data) # one cycle **AFTER** valid raised
-        # TODO set wen
-        st_ok = Const(1, 1)
+        #m.d.sync += self.d_in.byte_sel.eq(wen) # ditto
+        st_ok = self.d_out.valid # indicates write data is valid
         return st_ok
 
     def get_rd_data(self, m):