From: Luke Kenneth Casson Leighton Date: Fri, 8 Jan 2021 19:43:54 +0000 (+0000) Subject: add standards tags X-Git-Tag: convert-csv-opcode-to-binary~539 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3778efd1ba0be47cf99481d637c80757607366f0;p=libreriscv.git add standards tags --- diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index 7595ce738..f8c84cc36 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Simple-V Vectorisation for the OpenPOWER ISA **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review. diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn index 6b428cf31..2a302ea5d 100644 --- a/openpower/sv/16_bit_compressed.mdwn +++ b/openpower/sv/16_bit_compressed.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # 16 bit Compressed Similar to VLE (but without immediate-prefixing) this encoding is designed diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn index a5bfadde2..e91ce6ede 100644 --- a/openpower/sv/av_opcodes.mdwn +++ b/openpower/sv/av_opcodes.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Scalar OpenPOWER Audio and Video Opcodes the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA. However only by analysing those scalar opcodes *in* a SV Vectorisation context does it become clear why they are needed and how they may be designed. diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 0d6331be3..f80b17eda 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # bit to byte permute do j = 0 to 7 diff --git a/openpower/sv/byteswap.mdwn b/openpower/sv/byteswap.mdwn index b80de7ef3..194e48502 100644 --- a/openpower/sv/byteswap.mdwn +++ b/openpower/sv/byteswap.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Byte-swapping ## Byte-swapping Mux diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index f8faa6388..f6213096b 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # New instructions for CR/INT predication See: diff --git a/openpower/sv/fcvt.mdwn b/openpower/sv/fcvt.mdwn index 332e10ea7..27de2900e 100644 --- a/openpower/sv/fcvt.mdwn +++ b/openpower/sv/fcvt.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # SV FP Conversion OpenPOWER Scalar ISA requires that FP32 numbers be distributed throughout the bits of the underlying FP64 register such that at any time an FP64 opcode nay be used, without performing any kind of conversion, directly on that FP32 value. Likewise if precision is not important an FP32 opcode may be called on an FP64 value without conversion needed. diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 900e16f5a..ee4c11f6f 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # SV Load and Store Links: diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn index 3a4f3c3e6..0566c6f25 100644 --- a/openpower/sv/mv.swizzle.mdwn +++ b/openpower/sv/mv.swizzle.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # mv.swizzle Links diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn index ce7d1310b..0210b7d62 100644 --- a/openpower/sv/mv.vec.mdwn +++ b/openpower/sv/mv.vec.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Vector mv operations In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. This page covers those and more. [[svp64]] provides the Vector Context to also add saturation as well as predication. diff --git a/openpower/sv/mv.x.mdwn b/openpower/sv/mv.x.mdwn index 62249bb07..fcb7657f1 100644 --- a/openpower/sv/mv.x.mdwn +++ b/openpower/sv/mv.x.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # mv.x TODO diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn index 9778d1b89..85b59f8f5 100644 --- a/openpower/sv/propagation.mdwn +++ b/openpower/sv/propagation.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # SV Context Propagation [[!toc]] diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index be24a1609..efb05e898 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # OpenPOWER SV setvl/setvli See links: diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn index d5ebd7d93..1c0cfc6f3 100644 --- a/openpower/sv/sprs.mdwn +++ b/openpower/sv/sprs.mdwn @@ -1,20 +1,22 @@ -# CSRs +[[!tag standards]] -There are five CSRs, available in any privilege level: +# SPRs + +There are five SPRs, available in any privilege level: * MVL (the Maximum Vector Length) -* VL (which has different characteristics from standard CSRs) +* VL (which has different characteristics from standard SPRs) * SUBVL (effectively a kind of SIMD) * STATE (containing copies of MVL, VL and SUBVL as well as context information) -For Privilege Levels (trap handling) there are the following CSRs, +For Privilege Levels (trap handling) there are the following SPRs, where x may be u, s or h for User, Supervisor or Hypervisor Modes respectively: * (x)eSTATE (useful for saving and restoring during context switch, and for providing fast transitions) -The u/s CSRs are treated and handled exactly like their (x)epc +The u/s SPRs are treated and handled exactly like their (x)epc equivalents. On entry to or exit from a privilege level, the contents of its (x)eSTATE are swapped with STATE. @@ -47,7 +49,7 @@ Illegal values raise an exception. ## STATE -This is a standard CSR that contains sufficient information for a +This is a standard SPR that contains sufficient information for a full context save/restore. It contains (and permits setting of): * MVL @@ -59,7 +61,7 @@ full context save/restore. It contains (and permits setting of): * svoffs - the subvector element offset of the current parallel instruction being executed -The format of the STATE CSR is as follows: +The format of the STATE SPR is as follows: | Field | Name | Description | | ----- | -------- | --------------------- | diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index cfadc1a3d..8e2a8d098 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # SVP64 for OpenPOWER ISA v3.0B This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1B implementations has not yet been granted through the issuance of a v3.1B EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index 6210310b1..d9e401db7 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # SV Vector Operations. The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors) diff --git a/openpower/sv/vector_swizzle.mdwn b/openpower/sv/vector_swizzle.mdwn index 89984ffd2..34322e8a4 100644 --- a/openpower/sv/vector_swizzle.mdwn +++ b/openpower/sv/vector_swizzle.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # SV Vector Prefix Swizzle *