From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Jan 2022 00:10:11 +0000 (+0000)
Subject: add test for setting TB SPR, fix decode map for STATE regs
X-Git-Tag: sv_maxu_works-initial~547
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=377d6071904fa97af6476c278b837baf0f25717b;p=openpower-isa.git

add test for setting TB SPR, fix decode map for STATE regs
---

diff --git a/src/openpower/decoder/power_regspec_map.py b/src/openpower/decoder/power_regspec_map.py
index 6e93376d..71fbb282 100644
--- a/src/openpower/decoder/power_regspec_map.py
+++ b/src/openpower/decoder/power_regspec_map.py
@@ -104,20 +104,20 @@ def regspec_decode_read(m, e, regfile, name):
         SVSTATE = 1<<StateRegsEnum.SVSTATE
         if name in ['cia', 'nia']:
             # TODO: detect read-conditions
-            rd = RegDecodeInfo(Const(1), PC, 3)
+            rd = RegDecodeInfo(Const(1), PC, 5)
         if name == 'msr':
             # TODO: detect read-conditions
-            rd = RegDecodeInfo(Const(1), MSR, 3)
+            rd = RegDecodeInfo(Const(1), MSR, 5)
         if name == 'svstate':
             # TODO: detect read-conditions
-            rd = RegDecodeInfo(Const(1), SVSTATE, 3)
+            rd = RegDecodeInfo(Const(1), SVSTATE, 5)
         if name == 'state1':
-            rd = RegDecodeInfo(e.read_state1.ok, 1<<e.read_state1.data, 3)
+            rd = RegDecodeInfo(e.read_state1.ok, 1<<e.read_state1.data, 5)
 
     # FAST regfile
 
     if regfile == 'FAST':
-        # FAST register numbering is *unary* encoded
+        # FAST register numbering is *binary* encoded
         if name == 'fast1':
             rd = RegDecodeInfo(e.read_fast1.ok, e.read_fast1.data, 4)
         if name == 'fast2':
@@ -196,18 +196,18 @@ def regspec_decode_write(m, e, regfile, name):
         MSR = 1<<StateRegsEnum.MSR
         SVSTATE = 1<<StateRegsEnum.SVSTATE
         if name in ['cia', 'nia']:
-            wr = RegDecodeInfo(None, PC, 3) # hmmm
+            wr = RegDecodeInfo(None, PC, 5) # hmmm
         if name == 'msr':
-            wr = RegDecodeInfo(None, MSR, 3) # hmmm
+            wr = RegDecodeInfo(None, MSR, 5) # hmmm
         if name == 'svstate':
-            wr = RegDecodeInfo(None, SVSTATE, 3) # hmmm
+            wr = RegDecodeInfo(None, SVSTATE, 5) # hmmm
         if name == 'state1':
-            wr = RegDecodeInfo(e.write_state1.ok, 1<<e.write_state1.data, 3)
+            wr = RegDecodeInfo(e.write_state1.ok, 1<<e.write_state1.data, 5)
 
     # FAST regfile
 
     if regfile == 'FAST':
-        # FAST register numbering is *unary* encoded
+        # FAST register numbering is *binary* encoded
         if name == 'fast1':
             wr = RegDecodeInfo(e.write_fast1.ok, e.write_fast1.data, 4)
         if name == 'fast2':
diff --git a/src/openpower/test/spr/spr_cases.py b/src/openpower/test/spr/spr_cases.py
index 932542c0..8d396fe4 100644
--- a/src/openpower/test/spr/spr_cases.py
+++ b/src/openpower/test/spr/spr_cases.py
@@ -94,3 +94,19 @@ class SPRTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs)
 
+    def case_6_set_tb(self):
+        lst = [ "mtspr 268, 2",    # TB
+               "addi 1,0,0",
+               "addi 1,0,0",
+               "addi 1,0,0",
+               "addi 1,0,0",
+               "mfspr 1, 268", # TB
+                ]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x129518230011feed
+        initial_regs[2] = 0x123518230011fee0
+        initial_sprs = {'TB': 0x12345678,
+                        }
+        self.add_case(Program(lst, bigendian),
+                      initial_regs, initial_sprs)
+