From: Jakub Jelinek <jakub@redhat.com>
Date: Fri, 5 Feb 2021 09:39:03 +0000 (+0100)
Subject: i386: Fix up TARGET_QIMODE_MATH for many AMD CPU tunings [PR98957]
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37876976b0511ec96741f638f160874f2added0e;p=gcc.git

i386: Fix up TARGET_QIMODE_MATH for many AMD CPU tunings [PR98957]

As written in the PR, TARGET_QIMODE_MATH was meant to be set for all
tunings and it was the case for GCC <= 7, but as the number of
PROCESSOR_* enumerators grew, some AMD tunings (which are at the end
of the list) over time got enumerators with values >= 32 and
TARGET_QIMODE_MATH became disabled for them, in GCC 8 for 2
tunings, in GCC 9 for 7 tunings, in GCC 10 for 8 tunings, and
on the trunk for 11 tunings.

The following patch fixes it by using uhwis rather than uints
and gives them also symbolic names.

2021-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR target/98957
	* config/i386/i386-options.c (m_NONE, m_ALL): Define.
	* config/i386/x86-tune.def (X86_TUNE_BRANCH_PREDICTION_HINTS,
	X86_TUNE_PROMOTE_QI_REGS): Use m_NONE instead of 0U.
	(X86_TUNE_QIMODE_MATH): Use m_ALL instead of ~0U.
---

diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index a70f6edf7b0..cdeabbfca4b 100644
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -98,6 +98,8 @@ along with GCC; see the file COPYING3.  If not see
 #endif
 
 /* Processor feature/optimization bitmasks.  */
+#define m_NONE HOST_WIDE_INT_0U
+#define m_ALL (~HOST_WIDE_INT_0U)
 #define m_386 (HOST_WIDE_INT_1U<<PROCESSOR_I386)
 #define m_486 (HOST_WIDE_INT_1U<<PROCESSOR_I486)
 #define m_PENT (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM)
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index f0e07c0f81f..140ccb3d921 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -580,15 +580,15 @@ DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
    on simulation result. But after P4 was made, no performance benefit
    was observed with branch hints.  It also increases the code size.
    As a result, icc never generates branch hints.  */
-DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0U)
+DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", m_NONE)
 
 /* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic.  */
-DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0U)
+DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", m_ALL)
 
 /* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
    arithmetic to 32bit via PROMOTE_MODE macro.  This code generation scheme
    is usually used for RISC targets.  */
-DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0U)
+DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", m_NONE)
 
 /* X86_TUNE_EMIT_VZEROUPPER: This enables vzeroupper instruction insertion
    before a transfer of control flow out of the function.  */