From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 03:56:13 +0000 (-0700)
Subject: Fix RSTP
X-Git-Tag: working-ls180~1039^2~140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37a34eeb0438261f432917fb5d60a5320f56a8de;p=yosys.git

Fix RSTP
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index fe82b1307..055b3d6aa 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -438,7 +438,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 				st.ffPrstmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
 			}
 			else
-				cell->setPort("\\RSTP", State::S1);
+				cell->setPort("\\RSTP", State::S0);
 			if (st.ffPcemux) {
 				SigSpec S = st.ffPcemux->getPort("\\S");
 				cell->setPort("\\CEP", st.ffPcepol ? S : pm.module->Not(NEW_ID, S));