From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 22:40:17 +0000 (-0700)
Subject: Re-enable sign extension for C input
X-Git-Tag: working-ls180~1039^2~84
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37b0fc17e32d84698b6fa4ccbcff40155351e290;p=yosys.git

Re-enable sign extension for C input
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 5af48e4d2..ce75be0e9 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -322,10 +322,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 		opmode[5] = State::S1;
 
 		if (opmode[4] != State::S0) {
-			//if (st.postAddMuxAB == "\\A")
-			//	st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool());
-			//else
-			//	st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool());
+			if (st.postAddMuxAB == "\\A")
+				st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool());
+			else
+				st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool());
 			cell->setPort("\\C", st.sigC);
 		}