From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 3 Oct 2023 10:11:18 +0000 (+0100)
Subject: Added English Language description for stq instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37b56a279ff12ed4a1fa48220d96c3a44aa6652d;p=openpower-isa.git

Added English Language description for stq instruction
---

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index f443e817..07b1b534 100644
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -426,6 +426,25 @@ Pseudo-code:
     EA <- b + EXTS(DS || 0b00)
     MEM(EA, 16) <- RSp
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+
+    (DS||0b00). The contents of register pair RSp are
+    stored into the quadword in storage addressed by EA.
+
+    If RSp is odd, the instruction form is invalid.
+
+    The contents of an even-odd pair of GPRs is stored into
+    the quadword in storage addressed by EA as follows.
+    In Big-Endian mode, the even-numbered GPR is stored
+    into the doubleword in storage addressed by EA and
+    the odd-numbered GPR is stored into the doubleword
+    addressed by EA+8. In Little-Endian mode, the
+    even-numbered GPR is stored byte-reversed into the
+    doubleword in storage addressed by EA+8 and the
+    odd-numbered GPR is stored byte-reversed into the
+    doubleword addressed by EA.
+
 Special Registers Altered:
 
     None