From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Sep 2023 03:34:39 +0000 (-0700)
Subject: add unit test for mcrxrx
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37bb1fe61b26ed4957227af4224c4aeb4281624c;p=openpower-isa.git

add unit test for mcrxrx
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 90e3ac11..74615907 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -819,3 +819,26 @@ class ALUTestCase(TestAccumulatorBase):
                     programs[asm] = Program([asm], bigendian)
                 self.add_case(programs[asm], initial_regs,
                               initial_sprs=initial_sprs, expected=e)
+
+    def case_mcrxrx(self):
+        p = Program(["mcrxrx 3"], bigendian)
+        for i in range(16):
+            initial_sprs = {}
+            xer = SelectableInt(0, 64)
+            ov = bool(i & 8)
+            ov32 = bool(i & 4)
+            ca = bool(i & 2)
+            ca32 = bool(i & 1)
+            xer[XER_bits['OV']] = ov
+            xer[XER_bits['OV32']] = ov32
+            xer[XER_bits['CA']] = ca
+            xer[XER_bits['CA32']] = ca32
+            initial_sprs[special_sprs['XER']] = xer
+            # now construct the state
+            e = ExpectedState(pc=4)
+            e.ca = (ca32 << 1) | ca
+            e.ov = (ov32 << 1) | ov
+            e.crregs[3] = i
+
+            with self.subTest(ov=ov, ov32=ov32, ca=ca, ca32=ca32):
+                self.add_case(p, initial_sprs=initial_sprs, expected=e)