From: Kajol Jain <kajoljain797@gmail.com>
Date: Tue, 11 Jun 2019 10:09:17 +0000 (+0530)
Subject: arch-power: Added PIR register
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37c3c8db4dab1d87d1a7891dd0777f8442db5bb6;p=gem5.git

arch-power: Added PIR register

* Added PIR(Processor Identification Register).
* Added mfpir instruction to get content of register PIR.

Change-Id: I16b82684e7c9a5e5172f0395dd0a021791757425
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
---

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index b5e077f9b..3227d757e 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -628,7 +628,7 @@ decode PO default Unknown::unknown() {
                 0x3c9: mflpcr({{Rt = LPCR;}});
                 0x3E8: mfpvr({{ Rt = PVR; }});
                 0x3e9: mflpidr({{Rt = LPIDR;}});
-
+                0x3ff: mfpir({{ Rt = PIR;}}, [ IsPrivileged ]);
             }
             467: decode SPR {
                 0x004: mttfhar({{TFHAR = Rs;}});
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 7f2a9da8f..bc254cf74 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -145,6 +145,7 @@ def operands {{
     'IC': ('IntReg', 'ud', 'INTREG_IC', 'IsInteger' , 9),
     'VTB': ('IntReg', 'ud', 'INTREG_VTB', 'IsInteger' , 9),
     'HSPRG1': ('IntReg', 'ud', 'INTREG_HSPRG1', 'IsInteger' , 9),
+    'PIR': ('IntReg', 'uw', 'INTREG_PIR', 'IsInteger' , 9),
 
     # Setting as IntReg so things are stored as an integer, not double
     'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 3690fb641..e766fcd1c 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -64,7 +64,7 @@ const int NumIntArchRegs = 32;
 
 // CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR
 // and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 87;
+const int NumIntSpecialRegs = 88;
 const int NumFloatArchRegs = 32;
 const int NumFloatSpecialRegs = 0;
 const int NumInternalProcRegs = 0;
@@ -182,7 +182,8 @@ enum MiscIntRegNums {
     INTREG_ASDR,
     INTREG_IC,
     INTREG_VTB,
-    INTREG_HSPRG1
+    INTREG_HSPRG1,
+    INTREG_PIR
 };
 
 } // namespace PowerISA