From: lkcl <lkcl@web>
Date: Thu, 5 May 2022 16:15:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2437
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=37d6b437ef92284fe8c3d0e84c174641d73d88eb;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 54dc1489c..b8e13be08 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -4,7 +4,7 @@
 
 Inventing a new Scalar ISA from scratch is over a decade-long task including
 simulators and compilers: OpenRISC 1200 took 12 years to mature.
-A Vector or SIMD ISA to reach stable
+A Vector or Packed SIMD ISA to reach stable
 general-purpose auto-vectorisation compiler support has never been
 achieved in the history of computing, not with the combined resources of
 ARM, Intel, AMD, MIPS, Sun Microsystems, SGI, Cray, and many more.