From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Oct 2018 08:54:19 +0000 (+0100)
Subject: augment sv_addi test using macros
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3813886f51672da4d655c0af04b7f92cfc601a3a;p=riscv-tests.git

augment sv_addi test using macros
---

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index fb26814..d772874 100644
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -1,4 +1,22 @@
-#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec, packed) \
+#define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
-#define SV_PRED_CSR(type, regkey, zero, inv, regidx, active) \
+
+#define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))
+
+#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
+        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
+        csrrw  x0, 0x4c0, x1
+
+#define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+
+#define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
+#define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val
+
+#define SV_LD_DATA( reg, from, offs ) \
+        la      x1, from; \
+        lw      reg, offs(x1)
+
+#define TEST_SV_IMM( reg, imm ) \
+        li      x1, imm; \
+        bne     reg, x1, fail
diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index b6493bc..a78bcdc 100644
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -7,22 +7,27 @@ RVTEST_RV64U        # Define TVM used by program.
 
 # Test code region.
 RVTEST_CODE_BEGIN   # Start of test code.
-        csrrw   x0, 0x4f2, 2
-        la      x1, testdata
-        lw      x2, 0(x1)
-        la      x1, (testdata+8)
-        lw      x3, 0(x1)
-        li      x1, SV_REG_CSR(1, 2, 0, 2, 1, 0)
-        csrrw   x0, 0x4c0, x1
-        csrrw   x0, 0x4f0, 2
-        addi    x2, x2, 1         # Should be 42 into $2.
-        csrrwi  x0, 0x4f2, 0
-        csrrwi  x0, 0x4c0, 0
-        csrrwi  x0, 0x4f0, 0
-        li      x1, 42        # Desired result 1
-        bne     x2, x1, fail  # Fail out if doesn't match.
-        li      x1, 43        # Desired result 2
-        bne     x3, x1, fail  # Fail out if doesn't match.
+
+        SV_LD_DATA( x2, testdata   , 0)
+        SV_LD_DATA( x3, testdata+8 , 0)
+        SV_LD_DATA( x4, testdata+16, 0)
+        SV_LD_DATA( x5, testdata+24, 0)
+
+        SET_SV_MVL(2)
+        SET_SV_CSR(1, 3, 0, 3, 1, 0)
+        SET_SV_VL(2)
+
+        addi    x3, x3, 1
+
+        CLR_SV_CSRS()
+        SET_SV_VL(0)
+        SET_SV_MVL(0)
+
+        TEST_SV_IMM(x2, 1001) # should not be modified
+        TEST_SV_IMM(x3, 42)
+        TEST_SV_IMM(x4, 43)
+        TEST_SV_IMM(x5, 1002) # should not be modified
+
         RVTEST_PASS           # Signal success.
 fail:
         RVTEST_FAIL
@@ -33,9 +38,10 @@ RVTEST_CODE_END     # End of test code.
 .data
         .align 3
 testdata:
+        .dword 1001
         .dword 41
         .dword 42
-        .dword 43
+        .dword 1002
 
 # Output data section.
 RVTEST_DATA_BEGIN   # Start of test output data region.