From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 2 Mar 2022 13:26:15 +0000 (+0100)
Subject: Update CHANGELOG
X-Git-Tag: yosys-0.15~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3818e1160dae272b56692a86b6b0b55159a359a8;p=yosys.git

Update CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index dcb88d6fe..0b1bbc733 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -5,6 +5,11 @@ List of major changes and improvements between releases
 Yosys 0.14 .. Yosys 0.14-dev
 --------------------------
 
+ * Various
+    - clk2fflogic: nice names for autogenerated signals
+    - simulation include support for all flip-flop types.
+    - Added AIGER witness file co-simulation.
+
  * Verilog
     - Fixed evaluation of constant functions with variables or arguments with
       reversed dimensions
@@ -14,6 +19,13 @@ Yosys 0.14 .. Yosys 0.14-dev
 
  * SystemVerilog
     - Added support for accessing whole sub-structures in expressions
+ 
+ * New commands and options
+    - Added glift command, used to create gate-level information flow tracking
+      (GLIFT) models by the "constructive mapping" approach
+
+ * Verific support
+    - Ability to override default parser mode for verific -f command.
 
 Yosys 0.13 .. Yosys 0.14
 --------------------------