From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 13 Mar 2019 07:33:46 +0000 (+0000)
Subject: super is a keyword: replace with "supermode" in TLB and PermValidator
X-Git-Tag: div_pipeline~2297
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=382f1564ab31cd82ec9f1125b260205e21d30df0;p=soc.git

super is a keyword: replace with "supermode" in TLB and PermValidator
---

diff --git a/TLB/src/PermissionValidator.py b/TLB/src/PermissionValidator.py
index 6e8bee89..0808ab25 100644
--- a/TLB/src/PermissionValidator.py
+++ b/TLB/src/PermissionValidator.py
@@ -20,7 +20,7 @@ class PermissionValidator():
         # Input
         self.data = Signal(data_size);
         self.xwr = Signal(3) # Execute, Write, Read
-        self.super = Signal(1) # Supervisor Mode
+        self.supermode = Signal(1) # Supervisor Mode
         self.super_access = Signal(1) # Supervisor Access
         self.asid = Signal(15) # Address Space IDentifier (ASID)
 
@@ -36,7 +36,7 @@ class PermissionValidator():
                       & data[2] == self.xwr[1] \
                       & data[1] == self.xwr[0]):
                 # Supervisor Logic
-                with m.If(self.super):
+                with m.If(self.supermode):
                     # Valid if entry is not in user mode or supervisor
                     # has Supervisor User Memory (SUM) access via the
                     # SUM bit in the sstatus register
@@ -48,4 +48,4 @@ class PermissionValidator():
             with m.Else():
                 m.comb += self.valid.eq(0)
         with m.Else():
-            m.comb += self.valid.eq(0)
\ No newline at end of file
+            m.comb += self.valid.eq(0)
diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py
index 47381364..c1e8815e 100644
--- a/TLB/src/TLB.py
+++ b/TLB/src/TLB.py
@@ -35,7 +35,7 @@ class TLB():
         self.perm_validator = PermissionValidator(asid_size + pte_size)
 
         # Inputs
-        self.super = Signal(1) # Supervisor Mode
+        self.supermode = Signal(1) # Supervisor Mode
         self.super_access = Signal(1) # Supervisor Access
         self.command = Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2
         self.xwr = Signal(3) # Execute, Write, Read
@@ -109,7 +109,7 @@ class TLB():
                         # Execute, Read, Write
                         self.perm_validator.xwr.eq(self.xwr),
                         # Supervisor Mode
-                        self.perm_validator.super.eq(self.super),
+                        self.perm_validator.supermode.eq(self.supermode),
                         # Supverisor Access
                         self.perm_validator.super_access.eq(self.super_access),
                         # Address Space IDentifier (ASID)