From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 24 May 2020 07:52:56 +0000 (+0200)
Subject: litex_sim: override uart_name to sim only for serial.
X-Git-Tag: 24jan2021_ls180~297
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3833bc3ec38173a41474177614364e0b115d8761;p=litex.git

litex_sim: override uart_name to sim only for serial.

Using uart_name=crossover is useful to simulate crossover mode.
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 987681d3..4659985d 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -316,7 +316,6 @@ def main():
     builder_kwargs = builder_argdict(args)
 
     sim_config = SimConfig(default_clk="sys_clk")
-    sim_config.add_module("serial2console", "serial")
 
     # Configuration --------------------------------------------------------------------------------
 
@@ -324,7 +323,9 @@ def main():
     if "cpu_type" in soc_kwargs:
         if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
             cpu_endianness = "big"
-    soc_kwargs["uart_name"] = "sim"
+    if soc_kwargs["uart_name"] == "serial":
+        soc_kwargs["uart_name"] = "sim"
+        sim_config.add_module("serial2console", "serial")
     if args.rom_init:
         soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
     if not args.with_sdram: