From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 Oct 2014 08:31:54 +0000 (+0200)
Subject: Print "SystemVerilog" in "read_verilog -sv" log messages
X-Git-Tag: yosys-0.4~46
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3838856a9ee6debb05f39ad2c17d2eba95afd329;p=yosys.git

Print "SystemVerilog" in "read_verilog -sv" log messages
---

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 1e1cd852a..23d35f682 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -257,7 +257,7 @@ struct VerilogFrontend : public Frontend {
 		}
 		extra_args(f, filename, args, argidx);
 
-		log("Parsing Verilog input from `%s' to AST representation.\n", filename.c_str());
+		log("Parsing %s input from `%s' to AST representation.\n", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
 
 		AST::current_filename = filename;
 		AST::set_line_num = &frontend_verilog_yyset_lineno;