From: lkcl Date: Fri, 22 Oct 2021 09:48:26 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~3566 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=38396eb4d6df325af8681e21b5287dc04745d9ba;p=libreriscv.git --- diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn index 48cebda9e..a2b45f515 100644 --- a/3d_gpu/architecture/dynamic_simd/slice.mdwn +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -6,10 +6,10 @@ exactly the same `Shape` as the result of slicing the input `SimdSignal`'s corre ## Example code: ```python -a = SimdSignal(...) -a_s = a.sig # shorthand to make table smaller -b = a[3:6] -b_s = a.sig # shorthand to make table smaller +a_s = SimdSignal(...) +a = a_s.sig # shorthand to make table smaller +b_s = a_s[3:6] +b = b_s.sig # shorthand to make table smaller ``` ## `a`'s Elements: @@ -28,30 +28,30 @@ b_s = a.sig # shorthand to make table smaller ElWid: 8-bit - a_s[56:64] - a_s[48:56] - a_s[40:48] - a_s[32:40] - a_s[24:32] - a_s[16:24] - a_s[8:16] - a_s[0:8] + a[56:64] + a[48:56] + a[40:48] + a[32:40] + a[24:32] + a[16:24] + a[8:16] + a[0:8] ElWid: 16-bit - a_s[48:64] - a_s[32:48] - a_s[16:32] - a_s[0:16] + a[48:64] + a[32:48] + a[16:32] + a[0:16] ElWid: 32-bit - a_s[32:64] - a_s[0:32] + a[32:64] + a[0:32] ElWid: 64-bit - a_s[0:64] + a[0:64] @@ -73,37 +73,37 @@ So, slicing bits `3:6` of a 32-bit element of `a` must, because we have to match ElWid: 8-bit - b_s[21:24] - b_s[18:21] - b_s[15:18] - b_s[12:15] - b_s[9:12] - b_s[6:9] - b_s[3:6] - b_s[0:3] + b[21:24] + b[18:21] + b[15:18] + b[12:15] + b[9:12] + b[6:9] + b[3:6] + b[0:3] ElWid: 16-bit Padding - b_s[18:21] + b[18:21] Padding - b_s[12:15] + b[12:15] Padding - b_s[6:9] + b[6:9] Padding - b_s[0:3] + b[0:3] ElWid: 32-bit Padding - b_s[12:15] + b[12:15] Padding - b_s[0:3] + b[0:3] ElWid: 64-bit Padding - b_s[0:3] + b[0:3]