From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 19:43:02 +0000 (-0700)
Subject: Add test
X-Git-Tag: working-ls180~1163^2~18
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3839bd50f28a16f1253a56d5871465763e72180c;p=yosys.git

Add test
---

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
new file mode 100644
index 000000000..0b5403fa1
--- /dev/null
+++ b/tests/various/wreduce.ys
@@ -0,0 +1,22 @@
+
+read_verilog <<EOT
+module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
+    assign o = (i << 4) + j;
+endmodule
+EOT
+
+hierarchy -top wreduce_add_test
+proc
+design -save gold
+
+prep
+
+select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter